[−][src]Module stm32f103xx::dma1
DMA controller
Modules
| ccr1 | DMA channel configuration register (DMA_CCR) |
| ccr2 | DMA channel configuration register (DMA_CCR) |
| ccr3 | DMA channel configuration register (DMA_CCR) |
| ccr4 | DMA channel configuration register (DMA_CCR) |
| ccr5 | DMA channel configuration register (DMA_CCR) |
| ccr6 | DMA channel configuration register (DMA_CCR) |
| ccr7 | DMA channel configuration register (DMA_CCR) |
| cmar1 | DMA channel 1 memory address register |
| cmar2 | DMA channel 2 memory address register |
| cmar3 | DMA channel 3 memory address register |
| cmar4 | DMA channel 4 memory address register |
| cmar5 | DMA channel 5 memory address register |
| cmar6 | DMA channel 6 memory address register |
| cmar7 | DMA channel 7 memory address register |
| cndtr1 | DMA channel 1 number of data register |
| cndtr2 | DMA channel 2 number of data register |
| cndtr3 | DMA channel 3 number of data register |
| cndtr4 | DMA channel 4 number of data register |
| cndtr5 | DMA channel 5 number of data register |
| cndtr6 | DMA channel 6 number of data register |
| cndtr7 | DMA channel 7 number of data register |
| cpar1 | DMA channel 1 peripheral address register |
| cpar2 | DMA channel 2 peripheral address register |
| cpar3 | DMA channel 3 peripheral address register |
| cpar4 | DMA channel 4 peripheral address register |
| cpar5 | DMA channel 5 peripheral address register |
| cpar6 | DMA channel 6 peripheral address register |
| cpar7 | DMA channel 7 peripheral address register |
| ifcr | DMA interrupt flag clear register (DMA_IFCR) |
| isr | DMA interrupt status register (DMA_ISR) |
Structs
| CCR1 | DMA channel configuration register (DMA_CCR) |
| CCR2 | DMA channel configuration register (DMA_CCR) |
| CCR3 | DMA channel configuration register (DMA_CCR) |
| CCR4 | DMA channel configuration register (DMA_CCR) |
| CCR5 | DMA channel configuration register (DMA_CCR) |
| CCR6 | DMA channel configuration register (DMA_CCR) |
| CCR7 | DMA channel configuration register (DMA_CCR) |
| CMAR1 | DMA channel 1 memory address register |
| CMAR2 | DMA channel 2 memory address register |
| CMAR3 | DMA channel 3 memory address register |
| CMAR4 | DMA channel 4 memory address register |
| CMAR5 | DMA channel 5 memory address register |
| CMAR6 | DMA channel 6 memory address register |
| CMAR7 | DMA channel 7 memory address register |
| CNDTR1 | DMA channel 1 number of data register |
| CNDTR2 | DMA channel 2 number of data register |
| CNDTR3 | DMA channel 3 number of data register |
| CNDTR4 | DMA channel 4 number of data register |
| CNDTR5 | DMA channel 5 number of data register |
| CNDTR6 | DMA channel 6 number of data register |
| CNDTR7 | DMA channel 7 number of data register |
| CPAR1 | DMA channel 1 peripheral address register |
| CPAR2 | DMA channel 2 peripheral address register |
| CPAR3 | DMA channel 3 peripheral address register |
| CPAR4 | DMA channel 4 peripheral address register |
| CPAR5 | DMA channel 5 peripheral address register |
| CPAR6 | DMA channel 6 peripheral address register |
| CPAR7 | DMA channel 7 peripheral address register |
| IFCR | DMA interrupt flag clear register (DMA_IFCR) |
| ISR | DMA interrupt status register (DMA_ISR) |
| RegisterBlock | Register block |